Staff Engineer, STA and Synthesis

Responsibilities

• Perform full-chip and block-level Static Timing Analysis (STA) across all modes and corners.
• Analyze and debug setup, hold, recovery, removal, clock gating, and signal integrity-related timing violations.
• Work closely with Physical Design, Synthesis, CTS, and Design teams to achieve timing closure.
• Develop and maintain timing constraints including SDC creation, validation, and signoff readiness.
• Drive timing closure through ECO implementation and timing optimization.
• Analyze timing impact due to process, voltage, and temperature variations.
• Support timing signoff for pre-layout and post-layout stages.
• Perform cross-functional reviews for timing convergence and provide recommendations.
• Generate timing reports and communicate closure status to project stakeholders.
• 7–10 years of experience in Static Timing Analysis (STA) and timing closure for block and/or full-chip designs.
• Strong understanding of CMOS fundamentals, timing concepts, and semiconductor design flow.
• Hands-on experience in setup/hold analysis, path-based analysis, OCV/AOCV/POCV, derates, and MMMC concepts.
• Good understanding of clock tree, clock uncertainty, latency, skew, and jitter.
• Experience in timing constraints development and debugging.
• Strong knowledge of SDC, timing exceptions, false paths, multicycle paths, and case analysis.
• Familiarity with timing closure techniques and ECO methodologies.
• Hands-on experience with industry-standard STA tools such as Synopsys PrimeTime or Cadence Tempus.
• Good scripting skills in Tcl, Perl, or Python.
• Ability to analyze and resolve timing violations independently.

Nice to have