Staff Engineer – SOC Design Verification

Opportunity

Job Requirements

• 7 to 10 years of hands-on experience in SoC Design Verification .
• Proven experience in SoC-level testbench architecture, test development, and test plan creation .
• Strong understanding of SoC design and verification methodologies .
• Hands-on proficiency in Verilog, System-Verilog, UVM, SVA, and PSS .
• Experience with industry-standard communication and interface protocols such as PCIe Gen5/6, USB 3.x/4, LPDDR4/5, QUP, eMMC, SD, and UFS .
• Knowledge of processor architectures including RISC-V, ARM, and NoC/Interconnect architectures .
• Strong understanding of power management concepts and power-aware verification methodologies .
• Exposure to Gate-Level Simulation (GLS) is highly desirable.
• Proficiency in scripting languages such as Python, Perl, TCL, or Bash for automation and productivity improvement.
• Hands-on experience with waveform debugging tools such as Verdi and strong root-cause analysis skills.
• Excellent communication, collaboration, and stakeholder management skills, with the ability to work effectively across cross-functional teams.
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