Staff design Verification Engineer

• Working with all stakeholders to ensure program success

Designation : Staff Engineer

No. of years experience - 8+

Minimum Qualifications

• Bachelor's degree in Engineering, Information Systems, Computer Science, or related field.

Following skill set is required:

• Thorough understanding of Digital design concepts

• Strong Debug, UVM, System Verilog

• Understanding of Bus protocols like AHB/AXI/ACE/ACE-Lite

• Understanding of multi-core ARMv8 CPU architecture, coherency protocols and virtualization

• Good understanding of DDR families (LP/PC) and generations (DDR2/3/4/5)

• Quick understanding of Specs and Standards and developing relevant and thorough test plans

• Monitors, scoreboards, sequencers and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved

• Candidates should be comfortable checking our builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug, Must be willing to dig into fail and understand what is happening

• Post-Si bring-up and HW-SW debug experience would be a plus. Knowledge & exposure to silicon debug tool chains would be an added advantage

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