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STA Lead Engineer
MediaTek
Bengaluru, IND
Full-time
Senior · 6+ years experience
Onsite
Discovered 3 weeks ago
PrimeTimeTempusTweakerPrimeClosureDMSAICC2
Free
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Role Overview
Job Responsibilities: -Work in the full STA cycle, from initial constraints validation to final GDS sign-off -Perform STA setup, convergence, reviews, and signoff for multi-mode, multi-voltage SoC and subsystem designs -Manage timing ECOs (DMSA, tweaker, PrimeClosure) and conduct logical equivalence checks (RTL to Netlist) -Validate and debug timing across multiple PVT conditions using tools such as PrimeTime and Tempus -Work closely with RTL, Synthesis, and Physical Design teams to influence floorplanning and CTS strategies for timing-optimized layouts -Partner with design, DFT, synthesis, technology, CAD, and physical implementation teams
Key Skills for This Role
PrimeTimeTempusTweakerPrimeClosureDMSAICC2
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Job Description
Job Responsibilities: -Work in the full STA cycle, from initial constraints validation to final GDS sign-off -Perform STA setup, convergence, reviews, and signoff for multi-mode, multi-voltage SoC and subsystem designs -Manage timing ECOs (DMSA, tweaker, PrimeClosure) and conduct logical equivalence checks (RTL to Netlist) -Validate and debug timing across multiple PVT conditions using tools such as PrimeTime and Tempus -Work closely with RTL, Synthesis, and Physical Design teams to influence floorplanning and CTS strategies for timing-optimized layouts -Partner with design, DFT, synthesis, technology, CAD, and physical implementation teams
Main Requirements and Qualifications
- Preferred Experience:
- 6+ years of relevant experience in STA and semiconductor design
- Experience in driving timing convergence at chip-level and hard macro level
- Expertise in STA fundamentals, AOCV/POCV concepts, CTS, and timing constraints
- Hands-on experience with STA tools: PrimeTime, Tempus, Tweaker
- Familiarity with ASIC back-end flows such as ICC2 and Innovus
- Experience in low-power synthesis and equivalence checks is a plus
- Knowledgeable in clock gating, power gating, and multi-voltage design techniques
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