greenhouse
Sr. Staff Physical Design Timing Engineer (STA)
Lightmatter
Boston, USA
Senior · 12+ years experience
Discovered 1 weeks ago
python
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Role Overview
We are hiring a Physical Design Timing Engineer to help drive backend digital execution for some of the leading photonics based interconnect solutions.
You will work alongside a team of world-class scientists and engineers in defining how the system will be optimized and trailblaze problems that are new to the industry.
If your passion is innovation, solving challenging technical problems and doing impactful work you should join our team.
In this job you will be responsible for timing constraints development, STA and timing closure on leading edge CMOS technologies and flows.
This includes synthesis through place and route, timing closure, and tapeout signoff.
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python
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About this role
We are hiring a Physical Design Timing Engineer to help drive backend digital execution for some of the leading photonics based interconnect solutions. You will work alongside a team of world-class scientists and engineers in defining how the system will be optimized and trailblaze problems that are new to the industry. If your passion is innovation, solving challenging technical problems and doing impactful work you should join our team.
In this job you will be responsible for timing constraints development, STA and timing closure on leading edge CMOS technologies and flows. This includes synthesis through place and route, timing closure, and tapeout signoff.
Responsibilities
- Drive the STA sign-off for our flagship Silicon photonics chips at various technology nodes.
- Analyze fab guidelines and work with the methodology team to incorporate sign off corners, margins, and derates into timing analysis flows and methodologies.
- Collaborate with the architecture, RTL, and DFT teams to analyze the timing complexities and develop consolidated timing modes and constraints for synthesis, along with PnR and chip timing sign-off flows.
- Analyze and understand the tradeoffs between power/performance and area goals to drive them into overall chip implementation flows.
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