Sr Staff Engineer EM/IR

Define and maintain robust EMIR methodologies using standard EDA tools like Ansys RedHawk-SC, or Cadence Voltus.

Work on enhancing flow and methods for faster convergence and covering critical gaps with changing signoff trends.

Cross functional: Support chip-package-system (CPS) integration and work alongside silicon package and interposer teams. Work closely with PnR on fixes needed for EMIR violations and left shift strategy for correct by construction methods Work with DFT teams to understand impact of DFT strategy on EMIR, assess/fix impact on IR from DFT patterns, provide guidelines for toggling activity in DFT modes, provide power estimation to ATE and board testing teams. Work proactively with EDA vendors to get resolution on Tool issues, track critical issues impacting project, initiate and track topics of long term and future interests. Work with flow teams to integrate new methods and fixes in to the flow that are impacting ongoing projects. Initiate work flows for long term and future interests.

Support chip-package-system (CPS) integration and work alongside silicon package and interposer teams.

Work closely with PnR on fixes needed for EMIR violations and left shift strategy for correct by construction methods

Work with DFT teams to understand impact of DFT strategy on EMIR, assess/fix impact on IR from DFT patterns, provide guidelines for toggling activity in DFT modes, provide power estimation to ATE and board testing teams.

Work proactively with EDA vendors to get resolution on Tool issues, track critical issues impacting project, initiate and track topics of long term and future interests.

Work with flow teams to integrate new methods and fixes in to the flow that are impacting ongoing projects. Initiate work flows for long term and future interests.

Leadership & Management Responsibilities

Team Guidance: Direct daily task allocation, monitor metrics, and manage project schedules to meet tapeout milestones.

Mentorship: Train junior and mid-level engineers in advanced-node power integrity challenges and scripting (TCL, Python).

Cross-Functional Collaboration: Partner with timing (STA), physical design, package/interposer and analog/SerDes integration groups to clear design bottlenecks.

Stakeholder Reporting: Communicate technical risks, execution progress, and mitigation paths to upper management on a regular basis.

Qualifications & Requirements

Experience: 12+ years of relevant semiconductor industry experience, with proven background in power integrity sign-off.

Technical Skills: Advanced expertise in RedHawk_SC, Voltus, PTPX alongside strong scripting proficiency (Python/TCL). Should have deep knowledge in EMIR domain. Should have good knowledge of adjacent domains like STA and inter-operation with those domains.

Education: Bachelor’s or Master’s degree in Electrical Engineering, VLSI, or a related electronics discipline.

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