Sr Staff Engineer, Design Verification

Job Responsibilities

• Coding of simulation infrastructure using SystemVerilog (UVM) & C/(ARM,RISC-V Assembly)
• SoC Level verification is a must.
• Actively involve in all stages of product development including specification, circuit design, circuit modeling, verification, design for test, and silicon debug.
• Set up UVM verification environment, develop, and verify self-tested test benches for Mixed Signal chips and sub-circuits.
• Use and Development of Advanced UVM/mixed-signal simulation techniques to enhance simulation efficiency.
• Generate Verification Plan from the Specifications using vManager
• Determine Coverage and design completeness requirements
• Generate random-constraint tests to cover all customer-use-models
• Create Assertions, cover-groups, checkers, monitors and automatic reporting
• Set-up and run regression reports
• Works diligently to accomplish project goals and meet schedule requirements
• Job Requirements
• BSEE (MSEE pref.) or equivalent with 10+ years professional industry experience in Digital multi core SoC verification.
• Experience in digital Verification.
• Mixed-signal Verification is plus.
• UVM testbench creation, writing and implementation is a plus.
• Proficient developing scripts (Shell, Perl, Python etc.), and Cadence SKILL language is plus
• Experience with RN(Real Number)/Digital top-level modeling and verification methodology to speed up simulation (understanding accuracy/speed tradeoff and interfaces)
• Must be able to work independently with limited supervision and work closely with team.
• Work from office.
• Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.