SR ENGINEER, DDEG Design Methodology

Role Overview

Responsibilities

• Use AI-based tools, agentic workflows, and automation frameworks to accelerate verification.
• Assist with DRAM design verification test cases, testbenches, and related components.
• Validate AI outputs against specifications, simulations, waveforms, assertions, and coverage reports.
• Simulate, analyze, and debug pre-silicon block-level and full-chip designs.
• Develop test cases and stimulus to increase functional coverage.
• Maintain test benches and test vectors, and run regressions for coverage analysis.
• Collaborate on verification flows, methodologies, and environments for advanced memory products.
• Guide new team members and engineers.

Qualifications and Skills

• Experience with SystemVerilog and PLI coding.
• Experience building UVM test benches.
• Experience in DRAM, SRAM, or another memory-related field.
• Experience in AMS verification and co-simulation.
• Proficiency with either SPICE or Verilog simulations.