Sr. Engineer - ASIC PD

Engineer will be responsible for working with teams on floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, signal integrity, physical verification and DFM *Engineer will be responsible for working with teams on executing the block level place and route assignments from Netlist through GDS flow *Interacting with design team with purpose to solve problems and propose physical design engineering ideas. * To Coordinate all timing budgeting required for physical design task with respective teams * To close STA timing across all corners and modes for blocks and should be able to generate ECO independently .