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Sr. Digital Implementation Engineer
Alifsemi
Irvine, USA
Full-time
Senior
Onsite
Discovered 1 weeks ago
VerilogTclPerlPythonCadenceDesign Compiler
Free
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VerilogTclPerl
Key Skills for This Role
VerilogTclPerlPythonCadenceDesign Compiler
Full Job Posting
- Run complete synthesis flow
- Define and document synthesis (including DFT insertion) methodology and scripts/flows
- UPF flow for defining power intent (at block and chip level)
- RTL and Netlist hand-off checks (LEC)
- Interface with Physical Design for floor-planning and timing closure
- Assist with design partitioning and floorplan.
- Analyze STA results and facilitate RTL changes and Timing ECOs with front-end and back-end teams
- Significant experience with ASIC Synthesis Flow, Constraint Generation/Validation and Timing Closure
- Familiarity with DFT (Tessent) and back-end (Cadence) tools Hands-on experience with digital logic synthesis for power and area optimization
- Experience in low power design issues, tools, and methodology including UPF power intent specification
- Proficient in Verilog/SV/Tcl/Perl/Python
- Highly motivated to debug and resolve CAD tool flow issues
- Self-starter with good analytical, problem solving and communication skills
- Bachelor’s degree in Electrical Engineering, a related discipline, or equivalent experience.
- Strong expertise with Design Compiler or Genus.
- Experience with IP integration
- Experience with Synthesis, LEC, DFT, BIST
- Experience with Cadence Timing and ECO Flow
- Experience with Clock Domain Crossing (CDC) Analysis
- Experience with timing corner selection and library models
- Proven track record of successful deep submicron technology node tapeout (including Silicon bring-up)
- Detailed hands-on knowledge of all aspects of timing closure (including OCV, noise, crosstalk, IR-drop, power/voltage domains/UPF, DFT)
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