oracle
Sr ASIC Physical Design Engineer
Nokia
Sunnyvale, USA
Full-time
Senior · 5+ years experience
Hybrid
USD 371000-371000 yearly / year
Discovered 2 weeks ago
Cadence InnovusSynopsys IC CompilerMentor Graphics OlympusTCLPerlPython
Free
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Cadence InnovusSynopsys IC CompilerMentor Graphics Olympus
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Cadence InnovusSynopsys IC CompilerMentor Graphics OlympusTCLPerlPython
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Responsibilities
- Support specification, design, and implementation of digital hardware, applying design targets related to cost, yield, and reliability.
- Deliver hardware and software build-controlled productions releases, including EG main and update releases, service packages, maintenance updates, and customer design engineering.
- Manage product hardware and software evolutions through creation and release of documentation, change control management, and supplier and customer notifications.
- Participate in process and tool improvement initiatives.
- Maintain technical and design knowledge for assigned products and technologies.
- Ensure application and maintenance of quality engineering standards.
- Troubleshoot electronic engineering problems and apply the software care process when needed.
- Provide technical guidance and act as a subject matter expert to organization units and lower-level support teams.
- Determine project needs, including resource management and work allocation.
- Confer with customers to manage technical requirements. #LI-DNI
Qualifications
- Bachelor’s degree in Computer Science, Electrical Engineering, Electronic Engineering, or a related field, and 7 years of related work experience (5 years of which must be postbaccalaureate, progressive related work experience).
- Alternatively, will accept a Master’s degree in Computer Science, Electrical Engineering, Electronic Engineering or a related field, and 5 years of related work experience.
- Must have 5 years of experience in physical design engineering;
- Must have 5 years of experience utilizing digital design and CMOS technology;
- Must have 5 years of experience in physical design flow, including: synthesis and floorplanning, placement, routing, clock tree synthesis, and physical verification;
- Must have 5 years of experience using EDA tools, including Cadence Innovus, Synopsys IC Compiler, or Mentor Graphics Olympus;
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