eightfold
Sr AMS Layout Engineer-DPG-LPDDR
Micron Technology, Inc.
Hyderabad, IND
Full-time
Senior · 6+ years experience
Onsite
Discovered 3 weeks ago
VXL
Free
Job Fit Check
Base Career helps you apply smarter for this job.
?%
Ready to ScanKey skills for this role
VXL
Key Skills for This Role
VXL
Full Job Posting
Our vision is to transform how the world uses information to enrich life for all .
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Roles and Responsibilities
- Own the custom analog and mixed signal layout of critical analog blocks for LPDDR PHYs, including critical Datapath, bias networks, IO analog frontends, and reference circuits, ensuring robustness across PVT, low noise coupling, and high matching accuracy.
- Execute high‑speed LPDDR interface layout (LPDDRx), addressing signal integrity challenges such as skew control, impedance matching, shielding, crosstalk mitigation, and jitter sensitivity in advanced nodes.
- 6+ years of solid hands-on experience in analog and mixed signal, high-speed serial links..
- Design and optimize array‑based layouts for LPDDR DQ/DQS byte lanes, CA lanes, and replica paths, ensuring strict symmetry, pitch matching, repeatability, and scalability across multi‑byte and multi‑channel configurations.
- Implement custom digital block layouts within the LPDDR PHY, including training logic, calibration engines, and test/debug circuitry, with careful consideration of clocking, congestion, and interaction with sensitive analog regions.
- Drive layout‑aware co‑design with circuit designers to meet timing, noise, IR, and EM requirements for mixed‑signal LPDDR blocks, incorporating parasitic awareness early in the design cycle.
- Apply best practices for power distribution, grounding, and isolation , including guard rings, deep‑N‑well usage, decoupling strategies, and domain separation to protect critical analog and high‑speed signals.
- Perform DRC/LVS closure , parasitic extraction reviews, and correlation with simulation results to ensure silicon‑accurate performance of high‑speed and analog‑intensive LPDDR blocks.
- Support post‑layout optimization and ECOs , resolving issues related to margin degradation, yield, and manufacturability while maintaining JEDEC compliance.
Apply for this job in 1 click
Skip the repetitive application forms
Install the Base Career Chrome Extension and autofill job applications across major job boards with your profile.
Trusted by over 500,000 job seekers on Base Career
More from this employer
More jobs at Micron Technology, Inc.
Principal Engineer/MTS – Member of Technical Staff, HIG-HBM Product System Engineering (Media Health Reliability)
, USA
SeniorFull-time
Discovered 1 weeks agoView →
Facilities Medium Voltage Electrical Maintenance Technician
Boise, USA
EntryFull-time
Discovered 1 weeks agoView →
Senior Manager, Front End Manufacturing Alignment
Boise, USA
SeniorFull-time
Discovered 1 weeks agoView →
Principal Engineer - Analog Design
Bengaluru, IND
Discovered YesterdayFull-time
Principal Engineer/MTS – Member of Technical Staff, HIG-HBM Product System Engineering (Media Health Reliability)
, USA
Discovered 1 weeks agoFull-time
AI Adoption & Change Navigator
, USA
Discovered 1 weeks agoFull-time
Principal HBM Design Architect
Richardson, USA
Discovered 1 weeks agoFull-time
Facilities Medium Voltage Electrical Maintenance Technician
Boise, USA
Discovered 1 weeks agoFull-time
Principal Design AI Engineer
San Jose, USA
Discovered 1 weeks agoFull-time
Senior Manager, Front End Manufacturing Alignment
Boise, USA
Discovered 1 weeks agoFull-time
Design Verification Engineer
Boise, USA
Discovered 1 weeks agoFull-time