eightfold
Software Engineer — RISC-V Random Test Generator & Assembler Infrastructure
Qualcomm Technologies, Inc.
Cupertino, USA
Full-time
Mid Level
Onsite
USD 167100-250700 yearly
Discovered 1 weeks ago
Free
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You will contribute to a Python-based random test generation (RTG) framework and its companion assembler library that together form the core of a RISC-V CPU design-verification toolchain.
The RTG drives a JIT-style, simulator- coupled generator that produces ELF binaries exercising the RVA23.1 ISA — including privileged modes, virtual memory, interrupts, vector, and cryptography extensions.
The assembler library provides the bit-accurate instruction encoding
layer that the RTG and other tools consume.
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About The Role
You will contribute to a Python-based random test generation (RTG) framework and its companion assembler library that together form the core of a RISC-V CPU design-verification toolchain.
The RTG drives a JIT-style, simulator- coupled generator that produces ELF binaries exercising the RVA23.1 ISA — including privileged modes, virtual memory, interrupts, vector, and cryptography extensions.
The assembler library provides the bit-accurate instruction encoding
layer that the RTG and other tools consume.
What You'Ll Do
- Implement new generation objects for RISC-V extensions; common micro-architectural scenarios; and complex data/control-flow composable idioms.
- Add instruction forms and encodings to the python companion assembler and verifying bit-level correctness against the RISC-V ISA spec.
- Write and tune generation themes which are knob-driven test profiles that compose objects to improve RTL coverage.
- Work within the privileged-software stack: exception/interrupt handlers, page-table builders, PMP configuration, and IMSIC programming sequences.
- Work with ISS and RTL verification engineers to triage failures, add targeted regression scenarios, and adjust constraint logic (register allocators, address-space managers, data fillers).
What We'Re Looking For
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