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SoC Physical Design Engineer
Nokia
Louisa, USA
Full-time
Mid · 3+ years experience
Hybrid
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About the Role
SoC Physical Design Engineer will work on cutting edge ASIC implementation for Network Infrastructure Optical Network group.
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Responsibilities
- Perform physical implementation steps including floor planning, place and route, power/clock distribution, physical verification and timing closure at block level as well as full chip
- Work with logic designers & Hardware team to drive feasibility studies and explore design trade-off for physical design closure
- Perform technical evaluations of IP vendors, process nodes and provide recommendations
- Develop physical design methodologies and automation scripts for various implementation steps from Synthesis to GDSII
- Perform static timing analysis, create timing constraints and validation, critical path analysis, timing closure and timing sign-off
- Perform Physical verification and IR/EM analysis on blocks as well as top
- - Perform physical implementation steps including floor planning, place and route, power/clock distribution, physical verification and timing closure at block level as well as full chip - Work with logic designers & Hardware team to drive feasibility studies and explore design trade-off for physical design closure - Perform technical evaluations of IP vendors, process nodes and provide recommendations - Develop physical design methodologies and automation scripts for various implementation steps from Synthesis to GDSII - Perform static timing analysis, create timing constraints and validation, critical path analysis, timing closure and timing sign-off - Perform Physical verification and IR/EM analysis on blocks as well as top
Qualifications
- 3+ years of experience in ASIC physical design flow and methodologies in 3/5 and 7nm process nodes
- Has solid knowledge of full design cycle from RTL to GDSII and understanding of underlaying concepts of IC design, implementation flows and methodologies for deep submicron design
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