SoC Physical Design Engineer
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Key skills for this role
Key Skills for This Role
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Qualifications
- 8+ years of experience in ASIC physical design flow and methodologies in 3/5 and 7nm process nodes
- Has solid knowledge of full design cycle from RTL to GDSII and understanding of underlaying concepts of IC design, implementation flows and methodologies for deep submicron design
- Experience with EDA Place & Route tools like Fusion Compiler or Innovus or similar tools and Timing tools like Primetime or similar
- Scripting experience in TCL, python or Perl
- Candidates must have a bachelor's degree or higher in Electrical/Electronics and Communication/VLSI/Microelectronics with very good academics
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