SOC Integration Engineer

MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies.

Drive the evolution of MatX's silicon architecture-to-design methodology by engineering scalable solutions for the seamless integration of all Subsystems into a comprehensive full-chip SOC RTL design.

Partner with SubSystem owners within the Design team to facilitate block integration and spearhead the development of the System-On-Chip (SOC) Top-level RTL.

Implement advanced automation for SOC top-level RTL integration and build processes to enable on-the-fly generation of SOC top-level RTL.

Collaborate closely with the Full Chip owner on the Physical Design team to incorporate necessary RTL modules and feedthroughs/highways, ensuring alignment with chip-level floorplan connectivity requirements within the SOC RTL.

Establish robust clock and reset methodologies through cross-functional collaboration with system, architecture, design, and physical design teams.

Define and support SoC-level timing constraints, ensuring rigorous validation against Subsystem design and physical design requirements.

Provide technical support to package and board teams by defining SOC pin requirements and facilitating the generation of interposer netlists.