SoC Design Verification Engineer

Role Overview

Compensation & Benefits

• At Velaura, we believe exceptional talent deserves exceptional rewards. Compensation for this role includes a base salary and very competitive equity compensation, allowing team members to share in the company’s long-term success.
• The base pay listed represents a good faith estimate that the Company reasonably expects to pay for this position at the time of hire. Actual compensation will depend on multiple factors, including the candidate's skills, qualifications, relevant experience, and geographic location.
• In addition to base salary and equity compensation, Velaura offers a comprehensive benefits package that may include medical, dental, and vision coverage; paid time off; flexible work arrangements; professional development opportunities; and other benefits designed to support the well-being and growth of our team.
• Velaura is committed to pay equity and transparency and regularly benchmarks compensation to ensure we remain competitive in the market.

Responsibilities

• Drive verification planning and execution for your assigned areas of the Velaura Physical AI SoC.
• Build and maintain SoC level simulation environments and flows for CPU based SoCs such as ARM or RISC-V.
• Verify boot flows, root of trust, security state transitions and firmware handoff.
• Verify clock and reset topology, power domains and low power behavior at system level.
• Verify IO and memory subsystem integration including PCIe and LPDDR.
• Run CDC and RDC analysis at SoC level and close findings with the design teams.
• Verify system level latency, bandwidth and QoS under representative workloads.
• Support SoC sign off criteria, coverage closure and tape out readiness.

Required Qualifications

• 10 or more years in design verification, including significant SoC level experience.
• Experience leading or participating in multiple SoC verification projects, including sign off and tape out.
• Experience with SystemVerilog, UVM, C and C++ and coverage driven verification at system level.
• Experience managing simulation flows on CPU based SoCs such as ARM or RISC-V.
• Knowledge of IO and memory subsystem IP such as PCIe and LPDDR5 or LPDDR6.
• Experience verifying boot sequences and root of trust.
• Experience verifying clock and reset topology at system level, with hands on use of CDC and RDC tools.
• Experience with low power verification tools and UPF based flows.

Preferred Qualifications

• Depth in one or more areas such as security, memory subsystem, interconnect or power management.
• Experience with HW and SW co verification and pre silicon software bring up.
• Experience with emulation and FPGA prototyping at SoC level.
• Experience with one or more of ISO 26262, IEC 61508, IEC 61511 or ISO 13849.
• Experience verifying QoS, latency sensitive or real time systems.
• Experience with post silicon bring up, debug and root cause analysis.
• Familiarity with robotics, drones, autonomous vehicles or industrial automation systems.
• Experience using AI assisted verification workflows to improve productivity and coverage.

Why Velaura?

Equal Employment Opportunity and Accommodations