SoC Design Verification Engineer

Make an Impact: Your work will directly contribute to building a high-performance compute accelerator for scientific, AI, and other applications.

Rewarding Compensation: We offer competitive salaries, benefits, and equity.

Flexibility: Benefit from a hybrid work environment in our Austin offices, with exceptional candidates considered for fully remote work.

Grow With Us: Contribute to the development and improvement of verification methodologies, tools, and automation scripts.

Develop and execute verification plans for complex SoC digital designs.

Create and maintain UVM/SystemVerilog based testbenches and environments.

Write, debug, and execute constrained-random and directed test cases.

Implement RISC-V ISA compliance tests.

Perform functional coverage analysis and close coverage gaps.

Perform regression runs, analyze failures, and drive bug closure.

Connect simulations to real user interfaces, stimulus generators, and checkers.

Collaborate closely with RTL design engineers, architects, and software teams.

Contribute to the development and improvement of verification methodologies and automation scripts.

Perform preliminary debug of discovered issues.

A Bachelor's or Master's degree in Electrical, Electronics, or Computer Engineering (or related field).

3+ years of hands-on experience in ASIC/SoC design verification.

Strong proficiency in SystemVerilog, UVM, and simulation tools (e.g., Xcelium).

Solid understanding of digital design fundamentals, RTL design, and synthesis flow.

Experience with functional coverage, assertions, and scoreboarding.