Base Career helps you apply smarter for this job.
Key skills for this role
We are looking for a skilled and hands-on Signal Integrity, Power Integrity, and Characterization (SIPI) Engineer to join our hardware team. In this role, you will own electrical characterization of high-speed SerDes interfaces and power delivery networks across our AI accelerator compute systems. You will build and scale test automation infrastructure capable of covering thousands of channels, while collaborating closely with SIPI engineers and board designers to influence and validate designs from early concept through production.
MatX's mission is to make the world’s best AI models run as efficiently as allowed by physics, bringing the world years ahead in AI quality and availability.
We are looking for a skilled and hands-on Signal Integrity, Power Integrity, and Characterization (SIPI) Engineer to join our hardware team. In this role, you will own electrical characterization of high-speed SerDes interfaces and power delivery networks across our AI accelerator compute systems. You will build and scale test automation infrastructure capable of covering thousands of channels, while collaborating closely with SIPI engineers and board designers to influence and validate designs from early concept through production.
Characterize high-speed SerDes interfaces (PCIe, Ethernet, custom protocols) including BER testing, eye diagram analysis, and PVT characterization
Tune and optimize SerDes Tx and Rx equalization settings
Perform channel characterization including insertion loss, return loss, and crosstalk measurements using VNA and time-domain reflectometry (TDR)
Develop and execute correlation methodologies to align simulation predictions with measured results; drive feedback loops to improve modeling accuracy
Skip the repetitive application forms
Install the Base Career Chrome Extension and autofill job applications across major job boards with your profile.
Trusted by over 500,000 job seekers on Base Career
More from this employer
, USA
, USA
, USA
, USA
, USA
, USA
, USA
, USA
, USA
Measure and analyze high-current power rail transient noise and dynamic voltage droop on complex accelerator power delivery networks
Characterize PDN impedance from board through package and silicon, and compare against target impedance specifications
Identify PDN design weaknesses and collaborate with power delivery and board design teams to define and validate mitigation strategies
Architect, develop, and maintain scalable test automation frameworks for Electrical Design Validation Testing (EDVT) across thousands of SerDes channels on multi-chip accelerator compute systems
Integrate lab instruments (oscilloscopes, BERTs, VNAs, power analyzers) into automated test flows using Python or equivalent scripting environments
Build robust data pipelines for test result collection, statistical analysis, and visualization to enable rapid triage and design decisions
Partner with SIPI engineers on optimization for advanced package designs, including die-to-die interconnects, bump arrays, and interposer structures
Collaborate with board designers on PCB stackup definition, trace routing rules, via optimization, and decoupling strategies for high-speed accelerator boards
Provide characterization data and actionable recommendations to influence layout guidelines, design rules, and future silicon/package revisions
5–10 years of industry experience in hardware characterization, SI/PI engineering
Bachelor's degree or higher in Electrical Engineering; advanced degree a plus
Deep understanding of high-speed SerDes architecture and operation — PHY layer fundamentals, equalization, jitter decomposition, and link margin analysis
Strong grasp of transmission line theory — wave propagation, impedance matching, reflections, skin effect, and dielectric loss
Solid understanding of PDN design principles — target impedance, resonance, bypass capacitor placement, and voltage regulator loop dynamics
Hands-on proficiency with lab equipment
Experience writing test automation scripts in Python (preferred)
Background in AI accelerator or GPU system validation
Familiarity with JEDEC or PCIe compliance testing methodologies
Experience with statistical process control (SPC) or large-scale data analysis for silicon characterization
Ability to do layout review for PCB, and advanced package design is a plus
AI semiconductor company designing high-throughput chips for large language models and frontier AI labs.
Visit company websiteJobs and hiring trendsUSD 120000-475000 yearly / year
Full-time
Senior · 5+ years experience
Hybrid
Apply faster on company sites with our extension.