Server CPU Physical Design Integration Engineer, Staff level - Cambridge, UK

Master’s degree in Electrical Engineering, Computer Engineering, Computer Science , or a related technical field with relevant experience in hardware engineering, CPU design, physical design, clock design, or implementation.

PhD in Electrical Engineering, Computer Engineering, Computer Science , or a related technical field with relevant experience in CPU design, physical implementation, clock design, or circuit-aware methodology.

The role is intended for experienced candidates and is open for Staff Engineer level.

We are especially interested in engineers who:

Have strong fundamentals in physical design, timing, power, routing, clocking, and layout verification .

Enjoy solving complex integration challenges across floorplanning, partitioning, power planning, clock distribution, timing closure, physical verification, and tapeout readiness .

Bring a structured, analytical, and data-driven approach to debug, convergence, signoff closure, and methodology improvement.

Communicate clearly and effectively across microarchitecture, RTL, circuit design, CAD, timing, SoC integration, IP, and physical design teams.

Are proactive in identifying risks, driving cross-functional issue resolution, and capturing learnings to improve future product cycles.

Show technical curiosity and a continuous-improvement mindset, including the ability to automate repetitive tasks and improve debug efficiency.

Can provide technical leadership while remaining hands-on in complex design closure and integration challenges.

Thrive in a collaborative, fast-paced engineering environment where technical depth, execution quality, and cross-team partnership are essential.

Cambridge is Qualcomm’s largest office in the UK, with approximately 400 team members across engineering, business strategy, and support functions. From an engineering perspective, the Cambridge site includes teams focused on RF and PMU analog design, digital design and verification, digital physical design, embedded software, packaging, and post-silicon validation. Target products include high-performance CPUs and GPUs, ultra-low-power IoT devices, and wearables such as smart glasses, smart watches, and earbuds.

The Nuvia Data Center CPU team is building advanced custom CPU technology for next-generation compute platforms. As a CPU Physical Design Integration Engineer , you will play a key role in taking complex CPU designs from Implementation through integration, verification and final tapeout readiness.

This role offers the opportunity to work on challenging aspects of CPU physical design integration, including floorplanning, partitioning, IP integration, power and clock distribution, timing convergence, physical verification, power integrity, and final layout database assembly. You will collaborate closely with architecture, RTL, CAD, circuit design, block-level physical design, SoC, and signoff teams to deliver high-frequency, power-efficient, manufacturable CPU products.

This is an opportunity to contribute to technically demanding data center CPU designs, influence physical design methodology across future product generations, and make a direct impact on world-class silicon products developed by a highly experienced engineering team in Cambridge.

Minimum Qualifications:

*References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.

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