SerDes RTL Design Engineer

• Proficient in logic design concepts and RTL coding using Verilog/System Verilog
• Proficient in micro-architecture and developing design specifications
• Proficient with design checker tools and/or functional verification tools
• Knowledge of synthesis flow and static timing analysis
• Knowledge of low power design and methodology
• Experience in design with multiple clock domains
• Experience in mixed signal design
• Experience with Python, Perl, TCL and/or other scripting language
• Experience with SerDes PHY (PMA/PCS) and/or high-speed I/O protocol is preferred

• Bachelor's or master’s degree in electrical engineering, computer engineering, or related field

LOCATION: San Jose, CA or anywhere in the US

This role is not eligible for visa sponsorship.

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Benefits offered are described: AMD benefits at a glance .

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.

AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.