Senior Verification Engineer, PCIE

Be responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.

Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.

Expected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.

You will be collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks.

B.Tech./ M.Tech or equivalent experience

5+ years of relevant experience

Experience in verification at Unit/Sub-system/SOC level and expertise in Verilog and SystemVerilog

Expertise in comprehensive verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA)

Experience in developing and working in functional coverage based constrained random verification environments

Background in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug

Excellent knowledge of PCIE protocol - Gen3 and above

Good understanding of the system level architecture of PCIE/CXL-based designs

Perl, Python or similar scripting and SW programming language experience

Good debugging and analytical skills