Senior Technical Staff Engineer - Analog Design

The Timing and Communication Group (TCG) is seeking a highly seasoned Senior Technical Staff Engineer – Analog Design to provide technical leadership, architectural direction, across the development of advanced analog and mixed-signal IPs for next-generation timing solutions. This position goes beyond block-level design — it requires a strategic thinker with deep analog expertise, the ability to define system-level approaches, and a track record of mentoring and guiding high-performance design teams

Key Leadership & Technical Responsibilities

Architectural Ownership • Define architecture, specifications, and design methodologies for high-performance analog IPs including PLLs, DLLs, ADCs, DACs, high-speed I/O interfaces, and other critical IPs used in TCG timing products. • Drive top-level mixed-signal system architecture, ensuring robust integration of analog blocks within complex SoC environments.

Technical Leadership • Provide senior-level guidance to the analog team; mentor junior and mid-level designers through design reviews, modeling strategy, simulation methodology, and silicon bring-up. • Serve as a technical thought leader by influencing design tradeoffs, modeling strategies, and verification approaches across projects.

Hands-On Expertise • Lead transistor-level design and advanced simulations for critical analog circuits across process corners and operating conditions. • Develop behavioral and Verilog-A models that ensure fast, accurate representation of analog IPs within mixed-signal SoC simulations. • Guide silicon validation, test planning, characterization, and system-level lab evaluation for new analog IP blocks.