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Own the technical architecture and roadmap for NVLink and high-performance interconnect firmware across next-generation GPU platforms — staying hands-on in C, C++, and Python on the highest-leverage problems.
Take end-to-end ownership of sophisticated interconnect features, driving seamless execution from design through final verification.
Architect correctness models, verification plans, and test cases — primarily in Python — to prove firmware functionality across both pre-silicon and post-silicon environments.
Shape silicon bring-up, design-for-debug, and program-level validation strategy with architecture, hardware, and design leads across Bangalore and US sites.
Define the verification methodology, engineering standards, and quality gates the team builds to — and the automation strategy that scales them.
Advance the team’s AI-assisted, agentic debug and root-cause tooling, raising how fast the team resolves the hardest failures.
Grow the team’s technical capability — mentoring engineers, raising the quality bar, and de-risking the hardest cross-generation problems before they land.
BS or MS degree (or equivalent experience) in Electrical Engineering, Computer Science, or a related field.
10+ years of experience in firmware or software development and verification.
Deep programming proficiency in Python, C, and C++, with strong command of object-oriented design.
Strong understanding of computer architecture, microprocessors, and microcontroller fundamentals.
Expert debugging and analytical skills that span the hardware/software boundary.
A track record of technical leadership — setting direction, mentoring engineers, and raising quality across a team.
Excellent collaboration and communication skills, with proven success in a multi-national, multi-time-zone environment spanning on-site and remote teams.
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Senior · 10+ years experience
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