Senior RTL Design Lead (156478)

Hands-on experience with Synopsys ZeBu platforms.

Good understanding of emulation architecture and flows.

Experience with emulation build, compilation, and runtime debug.

Knowledge of hardware-assisted verification methodologies.

Understanding of ASIC/SoC design and verification flows.

Knowledge of simulation-to-emulation migration.

FPGA/Prototyping (Preferred) Experience with FPGA prototyping platforms such as HAPS , VCU, or equivalent. Understanding of synthesis, timing closure, and partitioning concepts. Software & Scripting Python scripting for automation. Shell/TCL scripting for build automation and debug. Linux environment proficiency.

Experience with FPGA prototyping platforms such as HAPS , VCU, or equivalent.

Understanding of synthesis, timing closure, and partitioning concepts.

Software & Scripting Python scripting for automation. Shell/TCL scripting for build automation and debug. Linux environment proficiency.

Python scripting for automation.

Shell/TCL scripting for build automation and debug.

Linux environment proficiency.

Strong debugging and problem-solving skills.

Ability to work independently on complex emulation projects.

Excellent communication and customer interaction skills.

Quick learner with the ability to adapt to new tools and methodologies.