Senior RTL design engineer - SOC Intergration

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

MTS SILICON DESIGN ENGINEER

THE ROLE: We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Job Requirements: B.E/M.E/M.Tech or B.S/M.S in EE/CE with 6+ years of relevant experience ASIC design flow and direct experience with ASIC design in sub-20nm technology nodes Digital design and experience with RTL design in Verilog/SystemVerilog Circuit timing/STA, and practical experience with PrimeTime or equivalent tools Low power digital design and analysis Modern SOC tools including Spyglass, Questa CDC, Cadence Conformal, VCS simulation Working knowledge of C; embedded experience a plus TCL, Perl, Python scripting Version control systems such as Perforce, ICManage or Git Strong verbal and written communication skills Should have experience working in geographically dispersed team and should be a strong team player.

B.E/M.E/M.Tech or B.S/M.S in EE/CE with 6+ years of relevant experience

ASIC design flow and direct experience with ASIC design in sub-20nm technology nodes