Senior RTL Design and Integration Engineer, Google Cloud

Responsibilities

• Participate in Design, implementation and integration of chassis, subsystems and SoC. Technology migration of Standard, foundational and Third-Party Intellectual Property (3PIPs).
• Perform RTL coding for Subsystems/SoC integration, function/performance simulation debug, Lint/CDC/FV/UPF checks and quality check flows like Lint, CDC, RDC, VCLP.
• Participate in design debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams.
• Coordinate with various IP teams to meet schedule and quality requirements.
• - Participate in Design, implementation and integration of chassis, subsystems and SoC. Technology migration of Standard, foundational and Third-Party Intellectual Property (3PIPs). - Perform RTL coding for Subsystems/SoC integration, function/performance simulation debug, Lint/CDC/FV/UPF checks and quality check flows like Lint, CDC, RDC, VCLP. - Participate in design debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams. - Coordinate with various IP teams to meet schedule and quality requirements.

Minimum qualifications:

Preferred qualifications:

Qualifications

• Minimum qualifications: - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. - 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. - 8 years of experience in design, implementation and integration of chassis, subsystems and SoC. - Experience with logic synthesis for RTL code, performance, and power. - Experience with low-power design. Preferred qualifications: - Master's degree or PhD in Electrical Engineering or Computer Science or equivalent practical experience with 10 years of relevant industry experience. - Experience in owning medium complex SoC integration and QC. - Experience with scripting languages (e.g., Python or Perl). - Experience with tape outs and bring up (support). - Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies. - Good understanding of Verilog or System verilog language.