Senior Lead Post-Silicon validation Engineer - SMMU

Languages/Methodology: ARM assembly, C for bare-metal tests, Python/TCL/Perl for scripting.

Emu/FPGA: Veloce/RUMI

Versioning/CI: Perforce, Jira.

OS/Drivers: bare-metal frameworks.

Test plan completeness and functional/code coverage closure against SMMU spec and use-cases.

Defect discovery rate and escape rate (pre- vs. post-silicon).

Time-to-root-cause for complex issues; quality of triage documentation.

Regression stability and automation coverage.

Performance validation completeness vs. targets (latency, bandwidth, QoS).

Create tests for stage-1 and stage-2 translations, ASID/VMID rollover, TLB shootdowns, and context switch stress.

Validate device DMA through SMMU under NoC congestion and clock gating scenarios; confirm ordering and coherency guarantees.

Run JTAG-based bring-up sequences to verify SMMU registers, enable translations, and capture trace for fault analysis.

Automate validation: configure IOMMU groups, map/unmap devices, inject faults, and parse kernel logs for health signals.

B.E/B.Tech or M.E/M.Tech in EE/ECE/CS (or equivalent).

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