Senior IC Design Verification Engineer

Responsibilities:

• Verify breakthrough Ethernet/networking IP to be integrated into next-generation SoCs for automotive, industrial, and edge computing markets.
• Responsible for the architecture, design, and implementation of UVM Verification of hardware IP & System on Chip (SoC) products.
• Perform thorough trade-off analysis on performance and complexity.
• Work closely with IP architecture, design, and verification teams on planning and execution to ensure the IP is delivered on time and with the highest quality.
• Produce quality documentation for all phases of the project, including detailed IP functional and implementation specifications.
• Build the directed and random verification tests
• Debug test failures to determine the root cause; work with architect and design engineers to resolve defects and correct issues
• Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements
• Proactively drive continuous improvement in design and verification methodology.
• Job Qualifications:
• 5+ years of experience in IP & System on Chip (SoC) products.
• Thorough knowledge and expertise in System Verilog and UVM Verification.
• Strong understanding of IP & SoC development methodology and proficiency in verification tools.
• Strong Experience in EDA tools and scripting (Python, TCL, Perl, Makefile, Shell) used to build tools and flows for verification environments