Senior Hardware Engineer (RTL / High-Level Synthesis)

Code Metal is the leader in automated software engineering you can trust.

As AI writes more of the world's code, the bottleneck in software has shifted from writing code to verifying it works, and AI cannot verify its own work with certainty.

Code Metal takes a fundamentally different approach: constrain AI to what it does reliably, verify every step independently of the model using formal methods, and keep engineers in the loop on the decisions that matter.

The result isn't code that probably works — it's code that is provably correct, with auditable proof.

Customers including the U.S.

Air Force, L3Harris, RTX, and Toshiba use Code Metal to modernize legacy code, optimize performance on real hardware, and move prototypes to production, fast.

Founded in 2023 with offices in Boston and San Francisco, Code Metal is funded by Accel, Salesforce Ventures, B Capital, Smith Point Capital, J2 Ventures, Shield Capital, Overmatch, RTX, and others.

Learn more at codemetal.ai.

Code Metal is in the business of transpiling between different languages.

This includes the transpilation tools enabled by AI and modern verification techniques — bridging the gap between algorithm development and deployment to embedded systems.

We are currently looking for a senior hardware/software engineer interested in architecting and expanding our capabilities towards creating production-ready RTL from high-level algorithm descriptions.

This role focuses on HLS integration and RTL code generation.

You will be joining a team that values technical rigor, ownership, and collaboration across disciplines.

Develop C++ and post-HLS readability and optimization passes to produce human-auditable RTL

Leveraging Agentic AI and verification capability within Code Metal

Contribute to CI/CD qualification including automated RTL simulation, functional verification, and regression testing

3+ years of hands-on experience with writing RTL code or using High-Level Synthesis, including at least one commercial HLS tool (Catapult, Vitis HLS, Stratus, or equivalent)

Solid hardware modeling background regarding fixed-point arithmetic, bit-accurate types, synthesis pragmas and modeling trade-offs

Scripting experience in Python for development, toolchain automation and testing

Strong debugging and problem-solving skills

Experience with simulation and functional verification flows

Experience using Linux-based development environments

Solid understanding of RTL / VHDL

Understanding of FPGA architectural capabilities and constraints

Knowledge of verification methodologies and testbench development

Experience with DSP algorithms and applications using Python/MATLAB

Nice to Have:

Bonus: Interest in or familiarity with LLM-assisted code transformation and readability tooling

Experience with Git-based development workflows and CI/CD environments

Pay depends on experience, but we strive to be at the upper end of the salary range

Health care plan with 100% premium coverage, including medical, dental, and vision

401k with 5% matching

Paid Time Off (uncapped vacation, plus sick and public holidays)

Flexible hybrid or remote work arrangement

Relocation assistance for qualifying employees

Wage Transparency - The salary range for this role is not a guarantee of compensation or salary, as the final offer amount may vary based on factors including, but not limited to, individual proficiency, skills, experience, and location.

We are an equal opportunity employer.

US Citizenship may be required for certain project assignments involving security clearance.

Pursuant to the San Francisco Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records.