Senior FPGA Engineer

Lead the architecture, design, and implementation of FPGA solutions using Verilog HDL

Translate system‑level requirements into clear, maintainable RTL architectures

Own complete design blocks from concept through to deployed hardware

Review and guide Verilog written by other engineers, setting best practices

Define and contribute to verification strategies, including self‑checking testbenches

Support FPGA bring‑up, debugging and performance validation on real hardware

Work closely with hardware, RF, and embedded software teams to ensure clean integration

Contribute to technical planning and risk reduction for future designs Provide technical mentorship to junior and mid‑level engineers

Strong, demonstrable experience designing production FPGA systems in Verilog

Deep understanding of Clock‑domain crossing and reset strategies

Pipelined architectures and timing closure

FSM design, datapaths, and control logic

Experience with modern FPGA tools (e.g. Xilinx Vivado; Intel Quartus)

Confidence debugging across RTL, simulation and hardware Design and implementation of DSP blocks

Experience with RF or mixed‑signal systems ADCs/DACs, clocking architectures, JESD‑style interfaces

Digital modulation concepts

Familiarity with Linux/device tree configuration

Experience with Python‑based verification

Designing testable, simulation‑first architectures

Familiarity with high‑speed or SoC‑based FPGA platforms

Hands‑on lab experience with oscilloscopes, logic analyzers and RF test equipment

Competitive compensation and stock options

Private Medical & Dental

Cycle to work scheme

Lunchtime catering on site