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Senior Engineer (Level 2)
eInfochips
Noida, IND
Full-time
Senior · 8+ years experience
Onsite
Discovered 1 weeks ago
Cadence VirtuosoADE/MaestroSpectreHSPICECustomSimMentor Calibre
Free
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Role Overview
What we are looking for:
• Design Experience: 8–12+ years of hands-on experience in analog IC design.
• Circuit Architecture & Design: Architect and design high-performance analog/mixed-signal building blocks (e.g., PLLs, ADCs/DACs, LDOs, Bandgaps, SerDes/PHY, Op-Amps).
• EDA exposure: Custom Design/Schematic: Cadence Virtuoso (ADE/Maestro). Simulation: Spectre, HSPICE, or CustomSim. Physical Verification: Mentor Calibre (DRC/LVS/PEX) or Synopsys IC Validator. Reliability/Sign-off: Experience with Voltus, RedHawk, or similar power/IR integrity tools
• Multi-Node Design: Translate and optimize designs across different process geometries, including transition strategies from Planar (e.g., 28nm) to FinFET (e.g., 16nm, 7nm…) nodes.
• Simulation & Verification: Perform comprehensive pre-layout and post-layout simulations, including Monte Carlo, corner analysis, noise analysis, and reliability modeling (EM/IR/Aging/BTI/HCI).
• Methodology: Drive best practices in analog design methodology, including the adoption of automated design tools and script-based verification (Python/SKILL/Tcl).
Key Skills for This Role
Cadence VirtuosoADE/MaestroSpectreHSPICECustomSimMentor Calibre
Full Job Posting
Job Description:
What we are looking for:
Design Experience: 8–12+ years of hands-on experience in analog IC design.
Circuit Architecture & Design: Architect and design high-performance analog/mixed-signal building blocks (e.g., PLLs, ADCs/DACs, LDOs, Bandgaps, SerDes/PHY, Op-Amps).
EDA exposure: Custom Design/Schematic: Cadence Virtuoso (ADE/Maestro). Simulation: Spectre, HSPICE, or CustomSim. Physical Verification: Mentor Calibre (DRC/LVS/PEX) or Synopsys IC Validator. Reliability/Sign-off: Experience with Voltus, RedHawk, or similar power/IR integrity tools
Multi-Node Design: Translate and optimize designs across different process geometries, including transition strategies from Planar (e.g., 28nm) to FinFET (e.g., 16nm, 7nm…) nodes.
Simulation & Verification: Perform comprehensive pre-layout and post-layout simulations, including Monte Carlo, corner analysis, noise analysis, and reliability modeling (EM/IR/Aging/BTI/HCI).
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