Senior Engineer IP Verification - AMS Verification

Role Overview

Technical Skills

• In-depth understanding of analog and mixed-signal circuits is required.
• Experience with Virtuoso, PrimeSim/FinSim, HSPICE, Xcelium, SimVision, and WaveView is required.
• Experience debugging complex analog, digital, and mixed-signal circuits is mandatory.
• Hands-on experience writing Verilog, Verilog-A/MS, and RVM models is required.
• Hands-on experience building block-level and full-chip SPICE testbenches is required.
• Experience building co-simulation and mixed-signal verification environments is required.
• Hands-on experience with SystemVerilog, UVM, and SystemVerilog/PSL assertions is required.
• Perl or Python scripting skills are a plus.
• Previous DRAM memory-related experience is required.

Responsibilities

• Verify analog and mixed-signal IP and debug complex circuit behavior.
• Develop hardware models and SPICE testbenches across block and full-chip levels.
• Build mixed-signal verification environments and apply SystemVerilog/UVM methodologies.
• Explore and adopt approved AI tools for verification workflows, scripting, and methodology improvements.
• Maintain responsibility for technical decisions while using AI-assisted tools.
• Communicate effectively, debug issues, and work well in a team.