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Key skills for this role
Drive and use best practice for floor plan development. Ensure collaboration with designers and layout colleagues to accurately capture requirements, and review floor plan prior to routing to ensure cell dimensions, device placement and pin location are optimal for performance and area.
Use state-of-the-art layout techniques for matching accuracy, parasitic reduction and yield optimization.
Strong use of automation to improve turn around times, including skill programming, TCL, PERL etc.
Routing and verification (DRC, ERC, LVS) of block and circuit level layout.
Organize layout reviews and ensure management is well informed of time scale estimates, progress against project plans and any arising issues.
Demonstrate, and continue to develop, expertise in layout using deep submicron CMOS processes
Demonstrate, and continue to develop, expertise in the required CAD tools (Virtuoso XL / Calibre DRC, LVS & PEX / VCAR / VSR /PVS / R3D).
Mentor junior layout engineers whilst working on more complex tasks.
Follow methodology guidelines to ensure easy portability of IP across designs.
Help resolve issues (CAD / PDK / process) alongside colleagues in corporate engineering.
Suggest improvements to methodology and procedures.
Take proactive approach to driving own development plan, utilizing team members and internal development opportunities.
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Global provider of embedded semiconductor and system solutions.
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Senior · 3+ years experience
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