Senior Digital Verification Engineer

At Mythic, our Design Verification (DV) team is central to ensuring the correctness and reliability of our novel digital dataflow architecture, which includes a sophisticated scheduling subsystem, high-performance interconnect fabric, and advanced DMA engines that work together with our Analog Compute Engines to accelerate AI workloads. DV engineers collaborate closely with RTL design, architecture modeling, custom analog IP, compiler, emulation, and post-silicon teams to ensure the full system operates as intended.

Because today’s AI workloads are too large and intricate to be fully verified in hardware alone, our team takes creative and rigorous approaches—combining simulation, modeling, and innovative verification strategies—to prove that neural networks will function correctly and efficiently.

We welcome engineers at all levels of experience who are eager to tackle challenging verification problems and contribute to the success of our breakthrough AI hardware.

At Mythic, our Design Verification (DV) team is central to ensuring the correctness and reliability of our novel digital dataflow architecture, which includes a sophisticated scheduling subsystem, high-performance interconnect fabric, and advanced DMA engines that work together with our Analog Compute Engines to accelerate AI workloads. DV engineers collaborate closely with RTL design, architecture modeling, custom analog IP, compiler, emulation, and post-silicon teams to ensure the full system operates as intended.

Because today’s AI workloads are too large and intricate to be fully verified in hardware alone, our team takes creative and rigorous approaches—combining simulation, modeling, and innovative verification strategies—to prove that neural networks will function correctly and efficiently.

We welcome engineers at all levels of experience who are eager to tackle challenging verification problems and contribute to the success of our breakthrough AI hardware.

• Hands-on system-level and block-level verification.
• Development of test plans and coverage plans.
• Testbench development and execution using UVM or other advanced DV methodologies.
• Creation of verification infrastructure and flows.
• Leverage architecture models to help verify large AI network functionality on the design.
• Collaborate with RTL designers and architects to verify subsystems such as scheduling fabrics, interconnects, DMA engines, and memory controllers.