ashby
Senior DFT Engineer
Morse Micro
Sydney, AUS
Full-time
Senior · 5+ years experience
Onsite
Discovered 2 weeks ago
JTAGATPGMBISTDFT scriptingSynthesisSDF
Free
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JTAGATPGMBIST
Key Skills for This Role
JTAGATPGMBISTDFT scriptingSynthesisSDF
Full Job Posting
Your responsibilities would include
- Own end-to-end DFT for wireless SoCs, including architecture, implementation, verification, tapeout sign-off, silicon bring-up, and production support.
- Define DFT architecture and coverage goals, optimizing test quality, pattern count, power, area, and tester time/constraints.
- Architect and implement SCAN solutions, including chains, sub-chains, masking, compressors, decompressors, SDCs, and ensure post synthesis SCAN DRC clean
- Develop and integrate at-speed test methodologies using OPCG for intra- and inter-clock domain testing.
- Implement low-power DFT techniques such as power-aware scan, clock staggering, and test-point insertion to meet ATE/package limits.
- Own MBIST integration and diagnostics for all on-chip memories, including JTAG-based debug diagnostic flows.
- Implement and maintain IEEE 1149.1 JTAG/TAP, BSDL, IEEE 1500 wrappers, and DFT test-mode/pin-mux control.
- Integrate DFT for third-party hardened IPs (e.g. PLL, USB PHY, RRAM, FUSE), including wrapper design and vendor pattern integration.
- Generate and validate ATPG (stuck-at, transition, path-delay) and MBIST patterns, perform GLS with SDF, deliver WGL/STIL, and support first silicon ATE bring-up/debug.
- Drive silicon debug, yield analysis, DFT scripting / automation, and cross-functional collaboration with frontend, verification, PnR, and ATE in fast-paced tapeout programs.
Essential skills
- (you must have):
- Bsc/MSc/Phd in Electrical / Electronics / Communication Engineering or Computer Science
- 5+ years experience as a DFT Engineer
- Strong hands-on experience in scan insertion/stitching, ATPG setup, JTAG, simulation, debug, and scan DRC analysis
- Solid understanding of digital design fundamentals, including RTL coding and verification
- Proven expertise on hierarchical DFT methodologies is a plug
- Post-silicon debug and silicon bring-up experience
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