Senior DFT Design/Micro architect Engineer, Google Cloud

Responsibilities

• Develop DFT strategy and architecture (e.g., hierarchical DFT, DFT for High speed iOs, Analog DFT).
• Develop and drive die level DFT validation strategy and Complete all Test Design Rule Checks (TDRC) and Design changes to fix TDRC violations to achieve high-test quality.
• Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block, and other DFT IP blocks.
• Document DFT architecture, test sequences, and boot-up sequences associated with test pins.
• Generate and deliver the production and debug patterns to Post Silicon engineering team and run diagnosis for post silicon supports.
• - Develop DFT strategy and architecture (e.g., hierarchical DFT, DFT for High speed iOs, Analog DFT). - Develop and drive die level DFT validation strategy and Complete all Test Design Rule Checks (TDRC) and Design changes to fix TDRC violations to achieve high-test quality. - Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block, and other DFT IP blocks. - Document DFT architecture, test sequences, and boot-up sequences associated with test pins. - Generate and deliver the production and debug patterns to Post Silicon engineering team and run diagnosis for post silicon supports.

Minimum qualifications:

Preferred qualifications: