Senior Design Verification Engineer - Mumbai

We are hiring a Senior Design Verification Engineer to own functional verification for design blocks and subsystems.

You will build and maintain verification environments, drive coverage closure, and ensure silicon-quality signoff before tapeout.

• Develop and maintain UVM-based verification environments and testbenches
• Write test plans, directed and constrained-random tests, and functional/code coverage models
• Debug RTL and testbench issues, and drive bugs to closure with design teams
• Perform assertion-based verification (SVA) and formal verification where applicable
• Lead and mentor a team of 3-4 verification engineers
• Own verification signoff and regression health for assigned blocks
• Collaborate with design, DFT, and architecture teams on verification strategy

• 5+ years of hands-on experience in functional verification using UVM/SystemVerilog
• Strong understanding of coverage-driven verification methodology
• Experience with simulation, debug, and regression tools (VCS/Questa or equivalent)