Senior Design Lead (163006)
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Key skills for this role
Role Overview
B.Tech./M.Tech with 2 to 10 years of experience exclusively in DFT.
Hands-on experience to do scan insertion, ATPG coverage improvement, Pattern Generation/Simulation. Should have expertise on Simulation debug No-timing/Timing.
Hands-on Experience to do MBIST Insertion, Verification, Pattern generation. Thorough with Diagnostics and Repairability concepts.
Spy Glass experience to resolve DFT DRC at RTL stage is a must.
Good to have functional & integration knowledge of TAP controllers and JTAG
Must be aware of interface to ATEs, tester hand-off languages/TDL/Verilog and must know to drive/modify test procedures. Desirable to have experience in Post Silicon Debug on Tester.
Good at Communication. Compatible to work with India teams
Key Skills for This Role
Full Job Posting
Job Summary
B.Tech./M.Tech with 2 to 10 years of experience exclusively in DFT.
Hands-on experience to do scan insertion, ATPG coverage improvement, Pattern Generation/Simulation. Should have expertise on Simulation debug No-timing/Timing.
Hands-on Experience to do MBIST Insertion, Verification, Pattern generation. Thorough with Diagnostics and Repairability concepts.
Spy Glass experience to resolve DFT DRC at RTL stage is a must.
Good to have functional & integration knowledge of TAP controllers and JTAG
Must be aware of interface to ATEs, tester hand-off languages/TDL/Verilog and must know to drive/modify test procedures. Desirable to have experience in Post Silicon Debug on Tester.
Good at Communication. Compatible to work with India teams
Key Responsibilities
- B.Tech./M.Tech with 2 to 10 years of experience exclusively in DFT.
- Hands-on experience to do scan insertion, ATPG coverage improvement, Pattern Generation/Simulation. Should have expertise on Simulation debug No-timing/Timing.
- Hands-on Experience to do MBIST Insertion, Verification, Pattern generation. Thorough with Diagnostics and Repairability concepts.
- Spy Glass experience to resolve DFT DRC at RTL stage is a must.
- Good to have functional & integration knowledge of TAP controllers and JTAG
- Must be aware of interface to ATEs, tester hand-off languages/TDL/Verilog and must know to drive/modify test procedures. Desirable to have experience in Post Silicon Debug on Tester.
- Good at Communication. Compatible to work with India teams
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