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Senior ASIC Package Design Engineer

K2 Space
Seattle, USA
Senior · 5+ years experience
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Responsibilities

  • Define ASIC package architecture for FC-BGA and MCM solutions, including substrate stack-up, ball-map strategy, power delivery, signal breakout, and mechanical constraints.
  • Lead package-level trade studies across cost, performance, power integrity (PI), signal integrity (SI), thermal, manufacturability, and reliability.
  • Establish package design standards, methodologies, and best practices.
  • Drive detailed design of FC-BGA packages for high-pin-count ASICs with high-speed SerDes, dense power grids, and RF signal content.
  • Define and review substrate stack-ups, via strategies, impedance control, escape routing, and reference plane planning.
  • Partner with silicon, RF, and systems teams to co-optimize die floorplans and package interfaces.
  • Support package-level SI/PI strategy, including high-speed digital interfaces, power delivery network (PDN) design, and decoupling strategy
  • Lead thermal architecture at the package level, including lid selection, TIMs, heat-spreaders, and mechanical interfaces to system cooling.
  • Manage relationships with external packaging vendors, substrate suppliers, and OSATs.
  • Drive material selection, substrate technology choices, and assembly process optimization.

Qualifications

  • Bachelor’s degree in Packaging Engineering, Mechanical Engineering, Electrical Engineering, or a related field.
  • 5+ years of experience in ASIC package design, with deep expertise in FC-BGA.
  • Proven experience delivering high-pin-count, high-performance ASIC packages into production.
  • Strong understanding of substrate technologies and materials, SI/PI fundamentals at the package level, and thermal management for power-dense ASICs.
  • Fluent in SI/PI and EM simulation tools such as SIWave, HFSS, and ADS.
  • Experience working directly with OSATs and substrate vendors.
  • Knowledge of packaging qualification and test methodologies.
  • Nice to Have
  • Experience with MCM or heterogeneous integration (chiplets, interposers, advanced laminates).
  • Background in high-speed digital or mixed-signal SoCs.
  • Familiarity with aerospace, space, or high-reliability electronics.
  • If you don’t meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged!
  • If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know.
  • Export Compliance
  • As defined in the ITAR, “U.S. Persons” include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a “U.S. Person.”
  • The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a “U.S. person” as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.
  • Equal Opportunity
  • K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

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