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Semiconductor Manufacturing & Architecture Analyst

SemiAnalysis
Hillsboro, USA
Full-time
Mid · 3+ years experience
Onsite
Discovered 1 weeks ago
FIBSEM
Free

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We also offer three core products

Industry Models – we develop and publish industry models on accelerator shipments, datacenter demand and supply, GPU total cost of ownership, and more. We work with hyperscalers, neoclouds, many of the world’s largest hedge funds, and government agencies.

Core Research – our public equity markets product, geared towards financial investors, distills our deep technical research and knowledge into key insights on technology and product trends.

Consulting and Technical Due Diligence – We conduct custom research and project work to guide key strategic and investment decisions for the largest private‑equity funds, leading venture‑capital firms, companies across the AI and semiconductor ecosystem, and government agencies.

Position Overview

SemiAnalysis is scaling STEEL, our semiconductor teardown and characterization lab in Hillsboro, Oregon, to support deep research into the hardware shaping the AI and datacenter industry.

We are hiring a Competitive Analysis Engineer (Semiconductor Manufacturing & Architecture). This is a highly hands-on role focused on generating evidence-based technical insights through physical teardown, imaging, and analysis of leading-edge hardware.

You will work across the full lifecycle, from sample preparation to data interpretation, translating physical observations into clear, defensible conclusions on process technology, integration strategies, and design intent.

This role is ideal for individuals driven by curiosity, investigation, and technical rigor, with the ability to connect microscopic evidence to macro-level industry decisions. You will operate as a subject matter authority on current and next-generation semiconductor manufacturing for AI and datacenter systems.

Responsibilities

  • Conduct end-to-end teardown and characterization of AI and datacenter hardware, spanning package → die → transistor level
  • Perform hands-on sample preparation and analysis, including operating tools such as FIB, SEM, and related characterization equipment
  • Interpret imaging and analytical data to derive insights on process integration, materials, and design trade-offs
  • Analyze and document FEOL, BEOL, and advanced packaging trends across foundries, memory vendors, and OSATs
  • Identify generational technology shifts, competitive positioning, and trade-offs in manufacturing approaches
  • Apply Design Technology Co-Optimization (DTCO) principles to explain design/process decisions, cost implications, and performance outcomes
  • Produce high-quality technical research and written analysis, co-authoring publications for SemiAnalysis clients
  • Translate complex physical findings into clear, structured, and defensible narratives for a technical audience
  • Contribute to the development and expansion of lab capabilities, workflows, and analytical coverage

Requirements

  • 3+ years of experience in semiconductor-related roles, including: Process integration (FEOL / BEOL) Advanced packaging integration Silicon / hardware engineering OR a closely related domain with exposure to leading-edge nodes
  • Process integration (FEOL / BEOL)
  • Advanced packaging integration
  • Silicon / hardware engineering
  • OR a closely related domain with exposure to leading-edge nodes
  • Broad process familiarity across: CMOS logic Memory technologies (e.g., HBM, GDDR, 3D NAND) Emerging semiconductor technologies
  • CMOS logic
  • Memory technologies (e.g., HBM, GDDR, 3D NAND)
  • Emerging semiconductor technologies
  • Strong understanding of: Process integration and product architecture Design Technology Co-Optimization (DTCO) principles
  • Process integration and product architecture
  • Design Technology Co-Optimization (DTCO) principles
  • Demonstrated ability to: Reason from physical / structural evidence → process & design intent Distinguish between real signals vs artifacts in analysis
  • Reason from physical / structural evidence → process & design intent
  • Distinguish between real signals vs artifacts in analysis
  • Hands-on experience or strong aptitude in: Semiconductor sample preparation Analytical tools such as FIB, SEM, and related techniques
  • Semiconductor sample preparation
  • Analytical tools such as FIB, SEM, and related techniques
  • Core competencies: Strong technical writing and structured argumentation High curiosity, ownership, and investigative mindset Ability to work independently and close analytical loops end-to-end
  • Strong technical writing and structured argumentation
  • High curiosity, ownership, and investigative mindset
  • Ability to work independently and close analytical loops end-to-end

Nice to Have

Experience with advanced characterization techniques: TEM / STEM EDS / WDS EELS SIMS Atom Probe Tomography (APT)

TEM / STEM

EDS / WDS

EELS

SIMS

Atom Probe Tomography (APT)

Exposure to: Advanced packaging R&D (2.5D / 3D integration, hybrid bonding, high-speed interconnects) Failure analysis & fault isolation (nanoprobing, emission microscopy, laser/e-beam methods)

Advanced packaging R&D (2.5D / 3D integration, hybrid bonding, high-speed interconnects)

Failure analysis & fault isolation (nanoprobing, emission microscopy, laser/e-beam methods)

Proven ability to: Interpret micrographs and compositional data to infer process/design characteristics

Interpret micrographs and compositional data to infer process/design characteristics

Programming skills: Python for image analysis, data processing, or lab automation

Python for image analysis, data processing, or lab automation

Established industry network across semiconductor ecosystem (foundries, memory vendors, packaging players)

Growth Areas

This role offers strong upside into both technical depth and industry influence:

Develop into a recognized authority in semiconductor manufacturing and architecture, particularly for AI/datacenter hardware

Expand expertise across full-stack semiconductor analysis (materials → process → architecture → system impact)

Contribute directly to industry-shaping research and thought leadership published by SemiAnalysis

Gain exposure to cutting-edge technologies and competitive strategies across global semiconductor leaders

Grow into a lead contributor or domain specialist within STEEL lab capabilities (e.g., packaging, memory, process nodes)

Opportunity to influence research direction, lab investments, and analytical frameworks

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