RTL Design Lead

Design Lead works with hardware engineering teams to build complex chips, System-on-Chips (SoCs), and IP/Sub-system blocks. Guides microarchitecture definition, RTL design, verification, and physical implementation from conception through tape-out, balancing power, performance, area, and schedule goals. Key Responsibilities • Execution & Delivery: Drive end-to-end design development of IP/Sub-system blocks and SoCs to meet the Performance, Area, Power and Schedule targets. • Team Leadership: Manage, mentor, and set goals for a team of digital engineers involved in design, synthesis, and timing. • PPA Optimization: Oversee design reviews to optimize Power, Performance, and Area (PPA) metrics. • Cross-Functional Collaboration: Partner with architecture, verification, and physical design teams. • Sign-off & Debug: Drive resolution on complex bugs, logic issues, and sign-off checks. Core Technical Skills • Design Languages: Advanced proficiency in Verilog, System-Verilog, and scripting tools like Python or Perl. • Architecture Knowledge: Familiarity with ARM or RISC-V processors, bus protocols (AXI/AHB), and high-speed interfaces (PCIe, USB, DDR). • Sign-off Methodologies: Experience with Static Timing Analysis (STA), Clock Domain Crossing (CDC), and Logical Equivalence Checking (LEC).