RTL Design for Data Center Chassis

Main Requirements and Qualifications

• MS in Electrical Engineering/Computer Engineering or or related field.
• 5+ years of experience in designing transistor-level digital circuits.
• 3+ years of experience in hands on experience in architecting and designing chassis for data center silicon.
• Strong knowledge in SoC/Chip/Chiplet chassis: clock and reset, power and thermal management, out-of-band management, platform security, RAS, debug & test, eFuse control and distribution, and etc.
• Expert on designing with Verilog, SystemVerilog, Perl and Tcl script.
• Proficiency with EDA tools like VCS, Design compiler, and so on.
• Prior experience in all Front End activities and quality checks (eg: Lint, CDC...)
• Good understanding and working knowledge in other domains like DV and DFT, timing closure
• Able to provide timing constraints and work with PD teams to ensure RTL meets timing
• Strong debugging and scripting skills (Perl, Python, Tcl...)
• Salary range: $143,000- $244,000. Employee may be eligible for performance bonus, short and long term incentive programs. Actual total compensation will be dependent upon the individual's skills, experience and qualifications. In addition, MediaTek provides a variety of benefits including comprehensive health insurance coverage, life and disability insurance, savings plan, Company paid holidays, Sick Leave, Vacation time, Parental leave, 401K and more.
• MediaTek is an Equal Opportunity Employer that is committed to inclusion and diversity to all, regardless of age, ancestry, color, disability (mental and physical), exercising the right to family care and medical leave, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (includes pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation.
• #LI-WC2