RFIC Layout Engineer

Description

Minimum Qualifications

• Minimum requirement of a bachelors degree
• FinFet experience.

Preferred Qualifications

• Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS.
• Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing.
• Solid understanding of RC delay, electromigration, and coupling.
• Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD and WPE.
• High level proficiency in interpretation of CALIBRE DRC, ERC, LVS in FinFet Technology.
• Knowledge of CADENCE layout tools.
• Excellent communication skills.
• Scripting skills in PERL or SKILL.