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R&D Engineering, Staff Engineer (Design Verification/ VIP Verification Engineers)
Synopsys Inc
Noida, IND
Full-time
Mid-Senior
Onsite
Discovered 1 weeks ago
Verification IP developmentSystemVerilogUVM methodologyNVMe protocolsPCIeUSB
Free
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Verification IP developmentSystemVerilogUVM methodology
Role Overview
The role suits an experienced Verification IP engineer who focuses on protocol edge cases, coverage metrics, root-cause debugging, scalable verification architecture, and customer success.
Key Skills for This Role
Verification IP developmentSystemVerilogUVM methodologyNVMe protocolsPCIeUSB
Full Job Posting
About Synopsys
Synopsys provides engineering solutions spanning silicon to systems, including silicon design, IP, simulation, analysis, and design services.
Candidate Profile
The role suits an experienced Verification IP engineer who focuses on protocol edge cases, coverage metrics, root-cause debugging, scalable verification architecture, and customer success.
What You'll Be Doing
- Design, develop, and maintain Verification IP using SystemVerilog and UVM for AMBA, PCIe, USB, Ethernet, UEC, UAL, MIPI, and other industry-standard protocols.
- Build verification plans that map protocol specifications to testable scenarios, coverage goals, and corner-case strategies.
- Code sequences, test scenarios, and checkers for coverage-based functional and code verification.
- Debug complex simulation failures across multi-layer protocol stacks and customer integration environments.
- Enhance VIP products for performance, reusability, and scalability as protocols and use cases evolve.
- Support customers during VIP integration and deployment by troubleshooting issues and answering technical questions.
- Collaborate with Design IP, R&D, and field application teams on product roadmaps and customer needs.
What You'll Need
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