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Principal Silicon Photonics Layout Engineer
Neye-systems-inc.
Santa Clara, USA
Full-time
Senior · 8+ years experience
Onsite
USD 220000-290000 yearly / year
Discovered 1 weeks ago
PythonCalibreKLayoutGitLayout CIEDA
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PythonCalibreKLayoutGitLayout CIEDA
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- Functional Library Development: Architect and maintain a robust library of Python functions to generate parametric geometries.
- Production-Scale Layout: Execute full-chip assembly for high-volume manufacturing (HVM).
- Design for Test (DFT) Automation: Develop and implement automated functions for the insertion of optical/electrical test structures .
- Automated Routing: Develop scripts to automate complex optical routing and other design features via code.
- Physical Verification: Lead the DRC/LVS cleanup process using tools like Calibre or KLayout.
- Version Control & CI/CD: Utilize Git and “Layout CI” to manage the evolution of the function library and validate code changes.
- Production SiPh Experience: 8-12+ years of experience in high-complexity layout design with a track record of shipping Silicon Photonics designs to production. You must understand how layout decisions impact wafer-level yield and performance consistency.
- Code-Based Layout Mastery: Advanced proficiency in Python and experience with functional layout frameworks.
- Version Control Expertise: Expert mastery of Git.
- DFT Mindset: Demonstrated experience in placing and routing test structures for automated wafer-scale probing.
- Verification Tools: Expert-level debugging of DRC in the EDA ecosystem , with the ability to translate foundry rule decks into layout code constraints.
- Education: M.S. in Electrical Engineering, Physics, or Computer Science with a focus on Physical Design.
- Deep familiarity using AI tools (e.g., LLMs, copilots) to accelerate engineering workflows, debugging, and problem-solving.
- MEMS Layout: Experience designing layout functions for MEMS structures.
- Data-Driven Feedback: Ability to parse large-scale foundry PCM data to refine the function library parameters.
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