Principal Physical Design Engineer

We are looking for a Principal Physical Design Engineer to join the team. Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.

As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance.

To achieve this goal, the SCHIE team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware.

We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.

We are seeking a highly skilled and experienced Physical Design Engineer to join our dynamic team.

As a key member of our semiconductor design team, you will be responsible for physical design implementation and physical integration efforts to ensure the successful development of cutting-edge semiconductor products.

• As a Principal Physical Design Engineer, you will be responsible for Physical Design tasks at block, subsystem, sub-chip, and/or full-chip level. The tasks will include Floorplanning, Synthesis, Placement, CTS and custom clocking, Routing, Static Timing, Physical Verification, Formal Equivalency, Power Efficiency, IR-Drop, and EM. You may also be involved in Physical Design flow development/automation and evaluation of and recommendations for technology, IP, and vendor selection.
• Expected to drive PD team at block/Sub System / Sub Chip / SOC level to set and deliver quality results as per planned milestone goals.
• You are expected to be able to work with limited direction, have keen attention to detail, and be able to provide crisp status of progress, issues, and risks on the program to the management team. Occasional travel may be required.