Principal Engineer - Verification

• To play the role of Verification engineer at the Block level verification.

• Develop verification test plans from design specifications.

• Development of test environments using System Verilog and UVM verification methodologies.

• Integration with RTL and basic simulation bring-up for the design.

• Create multiple test cases as per test plan and launch regressions.

• Generate Code/Functional coverage, analyze coverage results and correlate with the test plan.

• Working the design team members to identify and quickly resolve problems with the design.

• Bring a self-motivated and enthusiastic approach that will achieve any new requirements and overcome all challenge