Principal Engineer, Digital Design

Role Overview

Key Responsibilities

• Lead complex IP and subsystem RTL development within MCU SoCs against performance, power, and area targets.
• Drive micro-architecture definition and high-level digital design for assigned blocks.
• Support SoC integration with subsystem views and documentation for back-end and design verification teams.
• Own lint, CDC, and RDC quality checks and support functional verification.
• Collaborate with architecture, verification, physical design, and software teams on specifications and integration.
• Mentor junior engineers and contribute to RTL coding guidelines and process improvements.

Required Qualifications

• Bachelor’s degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering, or a related technical field.
• At least 15 years of hands-on digital IC or ASIC design experience with a record of delivering high-quality silicon.
• Strong RTL design expertise using Verilog or VHDL.
• Understanding of digital design principles, timing analysis, clocking, resets, and verification methodologies.
• Experience with EDA tools for synthesis, simulation, and static timing analysis.