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Principal Engineer , DFT
Renesas Electronics
Hyderabad, IND
Full-time
Mid-Senior
Onsite
Discovered 3 weeks ago
Design-for-test (DFT) architectureSoC and MCU test strategyScan testingATPGMBISTLBIST
Free
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Design-for-test (DFT) architectureSoC and MCU test strategyScan testing
Role Overview
Lead end-to-end design-for-test execution for advanced SoCs and MCUs.
Own the DFT lifecycle from test architecture definition through silicon bring-up and production test deployment.
Key Skills for This Role
Design-for-test (DFT) architectureSoC and MCU test strategyScan testingATPGMBISTLBIST
Full Job Posting
Role Overview
Lead end-to-end design-for-test execution for advanced SoCs and MCUs.
Own the DFT lifecycle from test architecture definition through silicon bring-up and production test deployment.
Key Responsibilities
- Define SoC-level DFT architecture and test strategy covering Scan, ATPG, MBIST, LBIST, JTAG/IJTAG, SSN, and test compression.
- Own test architecture, RTL design and integration, DFT verification, scan insertion, ATPG, coverage closure, and signoff.
- Drive silicon bring-up, debug, diagnosis, yield improvement, and production test enablement.
- Develop scalable DFT methodologies, automation frameworks, and best practices.
- Collaborate with Design, Verification, Physical Design, and Test Engineering teams.
- Provide technical leadership and mentor engineers across projects.
Technical Expertise
- DFT architecture and test planning.
- DFT RTL design and integration.
- Scan insertion, ATPG, MBIST, LBIST, JTAG/IJTAG, GLS, and signoff.
- Silicon bring-up, debug, diagnosis, and yield improvement.
- Hands-on experience with Tessent, Genus/Fusion Compiler, VCS/Xcelium, and Conformal/Formality.
- Automation and scripting with Python, TCL, Perl, or Shell.
Qualifications
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